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Preliminary
74LVT32244 * 74LVTH32244 Low Voltage 32-Bit Buffer/Line Driver with 3-STATE Outputs (Preliminary)
January 2001 Revised August 2001
74LVT32244 * 74LVTH32244 Low Voltage 32-Bit Buffer/Line Driver with 3-STATE Outputs (Preliminary)
General Description
The LVT32244 and LVTH32244 contain thirty-two noninverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit, 16-bit, or 32-bit operation. The LVTH32244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32244 and LVTH32244 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH32244), also available without bushold feature (74LVT32244). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Ordering Code:
Order Number 74LVT32244GX (Note 1) 74LVTH32244GX (Note 1) Package Number BGA96A (Preliminary) BGA96A (Preliminary) Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS500434
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Preliminary 74LVT32244 * 74LVTH32244 Connection Diagram Truth Tables
Inputs OE1 L L H Inputs OE2 L L H Inputs OE3 L L H (Top Thru View) Inputs OE4 L Description Output Enable Input (Active LOW) Inputs Outputs OE5 L L 5 I0 I2 I4 I6 I8 I10 I12 I15 I16 I18 I20 I22 I24 I26 I28 I31 6 I1 I3 I5 I7 I9 I11 I13 I14 I17 I19 I21 I23 I25 I27 I29 I30 OE8 L L H OE7 L L H Inputs I28-I31 L H X OE6 L L H Inputs I24-I27 L H X H Inputs I20-I23 L H X L H Inputs I16-I19 L H X I12-I15 L H X I8-I11 L H X I4-I7 L H X I0-I3 L H X Outputs O0-O3 L H Z Outputs O4-O7 L H Z Outputs O8-O11 L H Z Outputs O12-O15 L H Z Outputs O16-O19 L H Z Outputs O20-O23 L H Z Outputs O24-O27 L H Z Outputs O28-O31 L H Z
Pin Descriptions
Pin Names OEn I0-I31 O0-O31
Pin Assignments for FBGA
1 A B C D E F G H J K L M N P R T O1 O3 O5 O7 O9 O11 O13 O14 O17 O19 O21 O23 O25 O27 O29 O30 2 O0 O2 O4 O6 O8 O10 O12 O15 O16 O18 O20 O22 O24 O26 O28 O31 3 OE1 GND VCC1 GND GND VCC1 GND OE4 OE5 GND VCC2 GND GND VCC2 GND OE8 4 OE2 GND VCC1 GND GND VCC1 GND OE3 OE6 GND VCC2 GND GND VCC2 GND OE7
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance
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2
Preliminary
74LVT32244 * 74LVTH32244
Functional Description
The 74LVT32244 and 74LVTH32244 contain thirty-two non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs.
Logic Diagrams
Byte 1 Byte 2
Byte 3
Byte 4
VCC1 is associated with Bytes 1 and 2. VCC2 is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Preliminary 74LVT32244 * 74LVTH32244 Absolute Maximum Ratings(Note 2)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in High or Low State (Note 3) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage High-Level Output Current Low-Level Output Current Free Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
-32
64
-40
0
+85
10
C
ns/V
t/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 4) II(OD) (Note 4) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ Power Off Leakage Current Power Up/Down 3-STATE Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3.6 3.6 3.6 0 0 - 1.5V 3.6 3.6 3.6 3.0 Bushold Input Minimum Drive 3.0 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 A A A A A A VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 A A V V 2.0 0.8 TA = -40C to +85C Min Max -1.2 Units V V V Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO 5.5V
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Preliminary
74LVT32244 * 74LVTH32244
DC Electrical Characteristics
Symbol ICCH ICCL ICCZ ICCZ+ ICC Parameter Power Supply Current Power Supply Current Power Supply Current Power Supply Current VCC1 or VCC2 VCC1 or VCC2 VCC1 or VCC2 VCC1 or VCC2
(Continued)
VCC (V) 3.6 3.6 3.6 3.6 3.6 TA = -40C to +85C Min Max 0.19 5.0 0.19 0.19 0.2 mA mA mA mA mA Outputs High Outputs Low Outputs Disabled VCC V O 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Units
Conditions
Increase in Power Supply Current (Note 7) VCC1 or VCC2
Note 4: Applies to bushold versions only (LVTH32244). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 8)
TA = 25C Min Typ 0.8 -0.8 Max Units V V Conditions CL = 50 pF, RL = 500 (Note 9) (Note 9)
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = -40C to +85C Symbol Parameter CL = 50 pF, RL = 500 VCC = 3.3V 0.3V Min tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Output Enable Time Propagation Delay Data to Output 1.2 1.2 1.2 1.2 2.0 1.5 Max 3.5 3.5 4.0 5.0 4.7 4.2 VCC = 2.7V Min 1.2 1.2 1.2 1.2 2.0 1.5 Max 3.9 3.9 5.0 6.5 5.2 4.4 ns ns ns Units
Capacitance
Symbol CIN COUT
(Note 10)
Parameter Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Input Capacitance Output Capacitance
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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Preliminary 74LVT32244 * 74LVTH32244 Low Voltage 32-Bit Buffer/Line Driver with 3-STATE Outputs (Preliminary) Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A Preliminary
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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